1. Field of the Invention
The present invention relates to a NAND type flash memory or other semiconductor memory device having memory strings connected to bit lines and source lines via selection switches and to a signal processing system provided with such a semiconductor memory device, and more particularly relates to an increase of speed of a read operation of a semiconductor memory device.
2. Description of the Related Art
In a NAND type flash memory, a plurality of memory transistors are connected in series to form memory strings. Two memory strings share one bit contact and source line, whereby a higher integration is achieved.
In a general NAND type flash memory, an erase operation is performed by for example applying 0V to all word lines to which a selected memory string is connected, using all word lines to which unselected memory strings are connected as floating states, and applying a high voltage (20V) to the substrate of the memory array. As a result, electrons are drained from the floating gates to the substrate for only the memory transistors of the selected memory string. As a result, the threshold voltages of the memory transistors shift to the negative direction and become for example −3V.
Further, data is written in units of so-called “pages” of several hundred to several thousand bytes for memory transistors connected to the selected word line all together. Specifically, for example, a high voltage (for example 18V) is applied to the selected word lines, 0V is applied to bit lines to which memory transistors into which data is to be written (0 data) are connected, and a high level voltage (for example 3.3V) is applied to bit lines to which memory transistors for which the writing is to be prohibited (1 data) are connected. As a result, electrons are injected into the floating gates for only the selected memory transistors into which the data is to be written. The threshold voltages of the selected memory transistors shift to the positive direction and become for example about 2v.
In such a NAND type flash memory, data is both written and erased by an FN (Fowler Nordheim) tunnel current, so there is the advantage that supply of an operation current from a booster circuit in a chip is relatively easy and operation with a single power supply is easy. Further, since the data is written into the memory transistors connected to the selected word lines all together in units of pages, this is superior to a NOR type flash memory in the point of the write speed.
Further, data is read in a NAND type flash memory in units of randomly accessed pages by establishing the data stored in the memory cells through sense amplifiers and storing the data in a data register, then serially transferring the page data to the outside in units of 1 or 2 bytes. Specifically, for example, 0V is applied to the selected word lines, and a voltage of about 4V is applied to all unselected word lines. In the case of a NAND type flash memory, a plurality of memory cells are connected in series, therefore a reading current of the memory cells is smaller than that of the NOR type flash memory. Accordingly, the so-called “random access time” for establishing on the data stored in the memory cells through the sense amplifiers is long.